Design for Testability (DFT) Course

Start with digital logic, flip-flops, clocks, resets, and the path from RTL to a gate-level netlist. Consider how you would set an internal signal to a known value and observe its effect. These questions introduce controllability and observability: the foundations of a useful test strategy.

Practice focus: explain why a small sequential block is difficult to test through its normal inputs alone.

Follow how scan cells form a path for loading a state and reading back a response. Relate shift and capture operations to scan enable, test clocks, and reset control. Examine design-rule reports and investigate the conditions that prevent a scan structure from working as intended.

Practice focus: trace a scan operation and identify the first test-readiness issue to resolve.

Automatic test pattern generation searches for inputs that expose a modelled fault at an observation point. Explore stuck-at and transition faults, pattern generation, and fault simulation. Learn to ask what a report counts as detected, excluded, or unresolved before interpreting its coverage percentage.

Practice focus: explain how a pattern activates a fault and carries its effect to an observable response.

A workable test plan considers pattern volume, application time, and switching activity alongside coverage. Explore scan compression and the purpose of decompression and response compaction. Connect at-speed testing with launch and capture events, and examine why test clock behaviour needs careful review.

Practice focus: discuss a coverage, test-time, or power trade-off using the assumptions behind the result.

Study how built-in self-test brings test generation and response checking into the chip. Explore memory BIST controllers, address and data sequences, and how memory test differs from logic scan. Introduce logic BIST and the roles of stimulus generation and response signatures.

Practice focus: sketch a memory-test sequence and describe the behaviour each read or write is intended to check.

Learn how boundary-scan cells provide access around a device’s digital interfaces. Follow the purpose of the JTAG test access port, its controller, and the instruction and data paths. Place boundary scan within a wider test strategy rather than treating it as a replacement for internal logic or memory testing.

Practice focus: describe how a boundary-scan operation can help check an interconnect without relying on normal application software.

Bring a structured approach to simulation mismatches. Check the test setup, clock and reset sequence, scan connectivity, and unknown values before deciding what failed. Use logs and waveforms to locate the first divergence, then preserve the configuration needed to reproduce it.

Practice focus: write a short debug note that separates the symptom, supporting evidence, and proposed next check.

Bring together setup files, test constraints, tool runs, reports, and results. Use Linux and Tcl scripting concepts to organise repeated tasks and compare changes. Review the handoffs between DFT, RTL, physical design, and test teams, including the assumptions that need to travel with each deliverable.

Practice focus: present a reproducible run and explain remaining test limitations clearly.